MF Researcher Database

研究者データベース

詳細
魏　書剛
ウェイ　シュガン
知能機械創製部門
教授
Last Updated :2023/01/27

研究者基本情報

研究者

  • 氏名

    魏　書剛, ウェイ　シュガン

基本情報

  • 研究者氏名（日本語）

    魏, 書剛

  • 研究者氏名（カナ）

    ウェイ, シュガン

ホームページ

  • ホームページ1

    http://www.ps.eng.gunma-u.ac.jp/~wei-lab/wei/index.html

使用外国語

  • 発表に使用する外国語

    英語

  • 執筆に使用する外国語

    英語

所属

  • 群馬大学, 教授

学歴

  • 1990年, 東北大学, 工学研究科, 電子工学
  • 1982年, 中国ハルビン工業大学, 電気通信学部, 無線電工学
  • 1990年, 東北大学
  • 1982年

学位

  • 博士(工学)

所属学協会

  • IEEE
  • 日本音響学会
  • 電子情報通信学会

経歴

  • 1982年, 1984年
  • 1982年, 1984年, 中国ハルビン工業大学 助手

研究活動情報

研究分野

  • 情報通信, 計算機システム
  • 情報通信, 情報ネットワーク

研究キーワード

  • 計算機科学
  • 情報システム工学

論文

  • New Residue Signed-Digit Addition Algorithm, 魏書剛, 2020年, the Advances in Intelligent Systems and Computing book series, the Advances in Intelligent Systems and Computing, 1070, 1, 390, 396
  • FPGAを用いた音響信号レベル圧縮プロセッサの設計, 魏 書剛, 2003年01月, 電子情報通信学会研究会技報, VLD2003-66,77-82
  • SD数演算を用いた２進浮動小数点加算回路構成, 魏 書剛, 2002年, 電子情報通信学会信学技報, VLD2002-132,13-18
  • Modulo (2p±1) Multiplier Using a Three-Operand Modular Addition and Booth Recoding Based on signed-Digit Number Arithmetic, WEI SHUGANG, 2003年, Proceedings of 2003 IEEE International Symposium on Circuits and Systems
  • Modular Multipliors Based on a Modified Booth Recoding Method With Signed-Digit Number Representation, WEI SHUGANG, 2003年07月, Proceedings of 2003 International Technical conference on Circuits/Systems, Computers and Communications
  • Dynamic Range Compression Characteristics Using an Interpolatiog Polynomial for Digital Audio Systems, WEI SHUGANG, 2005年02月, IEICE TRANS. FUNDAMENTALS
  • Square-Rooting Algorithm Using Signed-Digit Arithmetic, WEI SHUGANG, 2005年07月, Proceedings of the 2005 International Technical Conference on Circuits/Systems, Computers and Communications
  • Number Conversions between RNS and Mixed-Radix Number System Based on Modulo $(2^{p} - 1)$ Signed-Digit Arithmetic, WEI SHUGANG, 2005年09月, ACM proceedings of the 2005 Symposuim on Integrated Circuits and Systems Design
  • New Booth Modulo $m$ Multipliers with Signed-Digit Number Arithmetic, WEI SHUGANG, 2005年12月, IPSJ Journal
  • Modulo $(2^{p} \pm 1)$ Multipliers Using a Three-Operand Modular Signed-Digit Addition Algorithm, WEI SHUGANG, 2006年02月, Journal of Circuits, Systems, and Computers
  • RSA暗号処理のための剰余演算回路, 魏 書剛, 2002年03月, 電子情報通信学会信学技報VLD2001, 9-16
  • SD数演算を用いた剰余数系ー重み数系変換回路, 魏 書剛, 2005年01月, 電子情報通信学会信学技報VLD2004, VLD2004-123,79-84
  • Fast Residue Arithmetic Multipliers Based on Signed-Digit Number System, WEI SHUGANG, 2001年09月, Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems
  • A New RNS to Mixed-Radix Number Converter Using Modulo $(2^{p} - 1)$ Signed-Digit Arithmetic, WEI SHUGANG, 2004年12月, Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems
  • Weighted-to-Residue and Residue-to-Weighted Converters with Three-Moduli $(2^n-1,2^n,2^n+1)$ Signed-Digit Architectures, WEI SHUGANG, 2006年05月, Proceedings of the 2006 IEEE Symposium on Circuits and Systems
  • Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted NumberConverters with Moduli Set (2^n-1,2^n,2^n+1), WEI SHUGANG, 2006年06月, IPSJ Journal
  • Residue Checker with Signed-Digit Arithmetic for Error Detection of Arithmetic Circuits, Shugang Wei, Kensuke Shimizu, 2003年01月, Journal of Cricuits, Systems and Computers
  • Modulo (2~p +-1) Multipliers Using Three-Operand Modular Addition and Booth Recoding Based on Signed-Digit Number Arithmetic, Shugang Wei, Kensuke Shimizu, 2003年05月, Proceedings of the 2003 IEEE Symposium on Circuits and Systems
  • Fast Modular Multiplication Using Booth Recoding Based on Signed-Digit Number Arithmetic, WEI SHUGANG, 2002年10月, Proceedings of 2002 IEEE Asia Pacific Conference On Circuits and Systems
  • Residue Checker with Signed -Digit Arithmetic for Error Detection of Arithmetic Circuits, WEI SHUGANG, 2003年, Journal of Circuits, Systems, and Computers
  • Residue Signed-Digit Arithmetic Circuit with a Complement of Mudulus and the Application to RSA Encryption Processor, WEI SHUGANG, 2002年09月, Proceedings of the 9th IEEE International Conference on Electronics, Circuits and Systems
  • A Booth Recording Method for Serial Modular Multipliers with Signed-Digit Number Representation, WEI SHUGANG, 2002年03月, Proceedings of the 2002 International Conference on Fundamentals of Electronics, Communications and Computer Sciences
  • A VLSI Implementation Method of a Compressor for Audio Systems, WEI SHUGANG, 2001年12月, J. Acoust. Soc. Jpn.(E)
  • Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System, WEI SHUGANG, 2001年10月, Proceedings of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
  • Parallel Modular Arithmetic Based on Signed-Digit Number System and the Application to Error Detection of Product-Sum Computation, WEI SHUGANG, 2001年10月, Proceedings of the 2001 International Symposium on Distributed Computing and Applications to Business, Engineering and Science Electronics, Circuits and Systems
  • Booth Memoryless Modular Multiplier with Signed-Digit Number Representation, WEI SHUGANG, 2004年12月, Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Syatems
  • FPGA Design of Audio Signal Level Compressor, WEI SHUGANG, 2004年12月, Proceedings of the 2004 International Conference on Circuits/Systems, Computers and Communications
  • Audio Dynamic Range Compression Characteristics Based on an Interpolating Polynomial, WEI SHUGANG, 2004年06月, Proceedings of the 2nd Annual IEEE Northeast Workshop on Circuits and Systems
  • A Multiplicative Inverse Algorithm Based on Modulo (2^p -1) Signed-Digit Arithmetic for Residue to Weighted Number Conversion, Shugang WEI, 2007年09月, Proceedings of 2007 IEEE International Symposium on Integrated Circuits
  • Acoustic Level Dynamic Compression Characteristics with FPGA Implementation, Shugang WEI, Wenhai XU, 2007年09月, Proceedings of the 7th WSEAS International Comference on Signal, Speech and Image Processing
  • 多値RSA暗号処理VLSIの性能評価, 魏 書剛, 1991年, 22/7,12-21
  • Signed-Digit数多値演算回路に基づくRSA暗号処理プロセッサの構成, 魏 書剛, 1990年, 21/6,21-31
  • 多段フィードフォワードNOR回路網の一設計法, 魏 書剛, 1987年, J70D/2,325-334
  • 多段フィードフォワードNAND回路網の設計, 魏 書剛, 1986年, J69-E/7,785-787
  • コンプレッサ/リミッタのDSPによる実現法, 魏 書剛, 1994年, 日本音響学会誌, 50/4,263-270
  • 状態遷移に基づくディジタル音響信号レベル表示回路の構成, 魏 書剛, 1995年, 日本音響学会誌, 51/4,291-298
  • A Novel Residue Arithmetic Hardware Algorithm Using a Signed-Digit Number Representation, WEI SHUGANG, 2000年, IEICE TRANS.INF. & SYST.
  • Residue Arithmetic Circuits Using a Signed-Digit Number Representation, WEI SHUGANG, 2000年, Proceedings of the IEEE 2000 International Symposium on circuits and Systems
  • Dynamic Acoustic Signal Processing, WEI SHUGANG, 2000年, Proceedings of 2000 World Multi Conference on Systemics, Cybernetics and Informatics
  • Compact Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits, WEI SHUGANG, 1999年, IEICE TRANS ELECTRONICS
  • Residue Arithmetic with a Signed-Digit Number System, WEI SHUGANG, 2000年, Proceedings of 4th International Conference on High-Performance Computing
  • Residue Arithmetic Circuits Based on the Signed-Digit Multiple-Valued Arithmetic Circuits, WEI SHUGANG, 1998年, IEEE Proceedings of 28th International Symposium on Multiple-Valued Logic
  • Realization of over-easy characteristic of compressor/limiter on a digital signal processor, WEI SHUGANG, 1997年, J. Acoust. Soc. Jpn. (E)
  • Modulo 2P-1 Arithmetic Hard wave Algorithm Using Signed-Digit Number Representation, WEI SHUGANG, 1996年, IEICE Japan
  • Realization of Dynamic Range Controllers on a Digital Signal Processor for Audio Systems, WEI SHUGANG, 1995年, J. Acoust. Soc. Jpn.(E)
  • Design of digital signal Level meter for audio systems based on the state transitions, WEI SHUGANG, 1995年, The Journal of the Acoustical Society of Japan(J)
  • Design of an ASIC for digital audio signal Level meters, WEI SHUGANG, 1994年, IEEE Proceedings of Seventh Annual IEEE International ASIC Conference and Exhibit
  • Design of Compressor/limiter on a digital signal processor, WEI SHUGANG, 1994年, The Journal of the Acoustical Society of Japan(J)
  • Synthesis of Multilevel Feed-Forward NAND Netuorks, WEI SHUGANG, 1986年, IEICE Japan
  • Synthesis of Multilevel Feed-Forward NOR Netuorks, WEI SHUGANG, 1987年, IEICE Japan
  • Design of an RSA Encryption Processor Based on the Signed-Digit Multiple-Valued Arithmetic Circuits, WEI SHUGANG, 1990年, Scripta Technica Inc
  • Performance Evaluation of a Multiple-Valued RSA Encryption VLSI, WEI SHUGANG, 1991年, Scriptn Technica Inc
  • Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation, WEI SHUGANG, 1999年, Proceedings of Ninth Great Lakes Symposium on VLSI
  • Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Mutiple-Valued Arithmetic Circuits, WEI SHUGANG, 1999年, Proceldings of the 12th International Conference on VLSI Design
  • FPGA implementation of gain calculation using a polynomial expression for audio signal level dynamic compression, Shugang Wei and Wenhai Xu, 2008年06月, J.Acoust. Soc. Jpn.(E)
  • Modular multipliers Using a Modified Residue Addition Algorithm with Signed-Digit Number Representation, Shugang Wei, 2009年03月, Lecture Notes in Engineering and Computer Science, International MultiConference of Engineers and Computer Scientists 2009
  • A New Residue Adder with Redundant Binary Number Representation, Shugang Wei, 2008年06月, Proceedings of the 6th Annual IEEE Northeast Workshop on Circuits and Systems
  • High-Speed Modular multipliers Based on a New Binary Signed-Digit Adder Tree Structure,, M. Zhang and S. Wei,, 2010年08月, Proceedings of Ninth International Symposium on Distributed Computing and Applications to Business, Engineering and Science
  • Residue-Weighted Number Conversion with Moduli Set {2p-1, 2p+1, 22p+1, 2p} Using Signed-Digit Number Arithmetic, C. Jiang and S. Wei, 2010年08月, Proceedings of Ninth International Symposium on Distributed Computing and Applications to Business, Engineering and Science
  • Efficient Residue Checker Using New Binary Modular Adder Tree Structure for Arithmetic of Error Detection, M. Zhang and S. Wei, 2011年07月, Proceedings of Eighth International Conference on Fuzzy Systems and Knowledge Discovery
  • ＳＤ数演算を用いた剰余数系ー２進数系変換アルゴリズム, 姜 長シュン、魏 書剛, 2010年01月, 電子情報通信学会研究報告, VLD2009-80, 71-76
  • ＳＤ数表現を用いた剰余演算回路設計とその性能評価, 張 明達、魏 書剛, 2010年01月, 電子情報通信学会研究報告, VLD2009-80
  • 最小ＳＤ数表現を用いた剰余演算とＦＩＲフィルタ回路への応用, 陳睿、田中勇樹、魏 書剛, 2011年01月, 電子情報通信学会研究報告, VLD2010-96, 75-80
  • 多項式表現のゲインを用いた音響信号レベル圧縮特性, 宮下達也、茂木和弘、魏 書剛, 2011年01月, 電子情報通信学会研究報告, VLD2010-96, 81-85
  • ＳＤ数演算を剰余数系―重み数系変換アルゴリズム, 新井聖哉、田中勇樹、魏 書剛, 2012年01月, 電子情報通信学会研究報告, 2011-110, 111-116
  • ２分木構造の剰余ＳＤ数演算を用いた算術演算エラー検出回路, 劉茜、茂木和弘、魏 書剛, 2012年01月, 電子情報通信学会研究報告, VLD2011-110, 117-121
  • A Sequential Modular Multiplication Algorithm Using Signed-Digit Additions, S. Wei, 2011年11月, IEEE Proceedings of TENCON2011
  • 剰余SD数の非零桁数を削減する変換アルゴリズム, 田中勇喜，魏書剛, 2012年07月, 第２５回　回路とシステムワークショップ, 156 - 159
  • Residue Signed-Digit Arithmetic and the Conversion between Residue and Binary Numbers for a Four-Moduli Set, S. Wei and C. Jiang, 2012年10月, Proceedings of 11th International Symposium on Distributed Computing and Applications to Business, Engineering and Science
  • An RSA encryption Implementation Method Using Signed-Digit Arithmetic Circuits, S. Wei, 2012年10月, IEEE Proceedings of 5th International Conference on Biomedical Engineering and Informatics
  • Residue-Binary Number Conversion Using Signed-Digit Arithmetic for a Three-Moduli Set, S. Wei, 2012年11月, IEEE Proceedings of TENCON2012
  • Residue-Weighted Number Conversion for Moduli Set {2^2n-1, 2^2n+1+1, 2^n} Using Signed-Digit Number, C. Jiang and S. Wei, 2012年06月, Proceedings of the 10th Annual IEEE Northeast Workshop on Circuits and Systems
  • Sequential Modular Multipliers Using Residue Signed-Digit Additions, S. Wei, 2012年08月, Journal of Communication and Computer
  • SD数の非零桁削減回路の改良, 田中 勇喜,魏 書剛, 2013年, 第２６回　回路とシステムワークショップ, 209-214
  • High-Speed Modular multipliers Based on a New Binary Signed-Digit Adder Tree Structure, M. Zhang and S. Wei, 2013年, Journal of Circuits, Systems, and Computers
    DOI
  • Residue-Weighted Number Conversion for Moduli Set {2^n-1, 2^n+1, 2^2n+1, 2^n} Using Signed-Digit Number, C. Jiang and S. Wei, 2013年, Journal of Circuits, Systems, and Computers
    DOI
  • ＳＤ数の２値符号化による算術演算回路の最適化設計と性能評価, 小林拓矢,茂木和弘,魏 書剛, 2013年, 電子情報通信学会研究報告, VLD-2012, 114, 39-44
  • ＳＤ数演算を用いたＲＳＡ暗号処理回路の設計と性能評価, 浅岡隼一,田中勇樹,魏 書剛, 2013年, 電子情報通信学会研究報告, VLD-2012, 115, 45-50
  • An Advanced Implementation of Canonical Signed-Digit Recoding Circuit, Tanaka, Yuuki; Wei, Shugang, 2013年11月, Journal of Communication and Computer
  • Efficient Implementations of Canonical Signed-Digit Recoding Algorithm, Tanaka Y., Zhang Y., Wei S, 2013年11月, Proceedings of ICDV2013
  • Recoding Algorithms for Minimal Signed-Digit Numbers in Residue Number System, Zhang Y., Tanaka Y. and Wei S, 2013年10月, IEEE Proceedings of TENCON2013
  • Residue-Weighted Number Conversion Using Signed-Digit Number for Moduli Set {2^2n-1, 2^2n+1+1, 2n}, Changjun Jiang, Shugang Wei, 2013年, Analog Integrated Circuits and Signal Processing
  • New Binary Modular Adder Tree Structure for Arithmetic of Error Checker of Arithmetic, Zhang M., Wei S., 2013年, Journal of Communication and Computer
  • Efficient squaring circuit using canonical signed-digit number representation, Tanaka, Yuuki; Wei, Shugang, 2014年, IEICE ELECTRONICS EXPRESS
    DOI
  • Residue Checker Using Optimal Signed-Digit Adder Tree for Error Detection of Arithmetic Circuits, Wei S, 2014年10月, IEEE Proceedings of TENCON2014
    DOI
  • Conversions between RNS and Mixed-Radix Numbers Using Signed-Digit Arithmetic, Wei S, 2014年12月, IEEE Proceedings of ISIC-2014
  • 剰余SD数演算回路を用いた算術演算誤り検出, 根間裕智,田中勇樹,魏 書剛, 2015年, 電子情報通信学会研究報告, VLD2014, 136, 151-156
  • An Efficient Diminished-1 Modulo 2n + 1 Multiplier Using Signed-Digit Number Representation, Tanaka Y. Wei S., 2015年11月, IEEE Proceedings of TENCON2015
  • Fast Signed-Digit Architectures of Conversions Between Residue and Binary Number Systems, Wei S, 2015年10月, Proceedings of 2015 IEEE Intl Conference on Electronics, Circuits, & Systems
  • 法2n-1上の剰余CSD数表現と剰余SD数乗算への適用, 田中勇樹,中村康資,魏 書剛, 2016年, 第29回回路とシステムワークショップ, 231-236
  • Residue Canonical Signed-Digit Representation Recoding Algorithms, Zhang　Y., Tanaka　Y., and Wei S., 2016年, Journal of Algorithms, Computer Network, and Security
  • 新しい剰余SD数加算アルゴリズムとRSA暗号処理への応用, 石川和誠,田中勇樹,魏 書剛, 2017年, 電子情報通信学会研究報告, VLD2016, 92, 147-152
  • New Modulo Multipliers Using Residue Signed-Digit Adders, Wei S, 2017年11月, IEEE Proceedings of TENCON2017
  • SD数演算に基づく4つの法を有する剰余数系?重み数系変換アルゴリズム, 山崎幸平,田中勇樹,魏 書剛, 2018年, 電子情報通信学会研究報告, VLD2017, 88, 83-88
  • Computation of Modular Multiplicative Inverses Using Residue Signed-Digit Additions, Wei S, 2016年10月, Proceedings of 2016 International SoC Design Conference
  • Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation, Tanaka, Yuuki;Suzuki, Yuuki;Wei, Shugang, 2020年, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 29, 9
    DOI
  • Realization of dynamic range controllers on a digital signal processor for audio systems., Wei Shugang;Shimizu Kensuke;Zhang Ming, 1995年, Ｊｏｕｒｎａｌ　ｏｆ　ｔｈｅ　Ａｃｏｕｓｔｉｃａｌ　Ｓｏｃｉｅｔｙ　ｏｆ　Ｊａｐａｎ　（Ｅ）, Journal of the Acoustical Society of Japan (E), 16, 6, 353, 362
  • 降下エキスパンジョンをもつ音響レベルエキスパンダのDSPによる実現, 魏 書剛;張 鳴;清水 賢資, 1995年03月, 日本音響学会研究発表会講演論文集, 1995, 1, 591, 592

MISC

  • A New Residue Adder with Redundant Binary Number Representation, Shugang Wei, 2008年, 2008 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, 157, 160
  • Modular Multipliers Using a Modified Residue Addition Algorithm with Signed-Digit Number Representation, Shugang Wei, 2009年, IMECS 2009: INTERNATIONAL MULTI-CONFERENCE OF ENGINEERS AND COMPUTER SCIENTISTS, VOLS I AND II, Vol. 1, 494, 499
  • Residue-weighted number conversion using signed-digit number for moduli set {2(2n) - 1, 2(2n+1) - 1, 2(n)}, Changjun Jiang,Shugang Wei, 2013年11月, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 77, 2, 105, 112
    DOI
  • Residue-weighted number conversion using signed-digit number for moduli set {2(2n) - 1, 2(2n+1) - 1, 2(n)}, Changjun Jiang,Shugang Wei, 2013年11月, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 77, 2, 105, 112
    DOI
  • RESIDUE-WEIGHTED NUMBER CONVERSION FOR MODULI SET {2(n)-1, 2n+1, 2(2n)+1, 2(n)} USING SIGNED-DIGIT NUMBER, Changjun Jiang,Shugang Wei, 2013年01月, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 22, 1, 1-17.
    DOI
  • RESIDUE-WEIGHTED NUMBER CONVERSION FOR MODULI SET {2(n)-1, 2n+1, 2(2n)+1, 2(n)} USING SIGNED-DIGIT NUMBER, Changjun Jiang,Shugang Wei, 2013年01月, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 22, 1, 1-17.
    DOI
  • HIGH-SPEED MODULAR MULTIPLIERS BASED ON A NEW BINARY SIGNED-DIGIT ADDER TREE STRUCTURE, Mingda Zhang,Shugang Wei, 2013年07月, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 22, 6, 1-18.
    DOI
  • HIGH-SPEED MODULAR MULTIPLIERS BASED ON A NEW BINARY SIGNED-DIGIT ADDER TREE STRUCTURE, Mingda Zhang,Shugang Wei, 2013年07月, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 22, 6, 1-18.
    DOI
  • High-Speed Modular Multipliers Based on a New Binary Signed-Digit Adder Tree Structure, Mingda Zhang,Shugang Wei, 2010年, PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON DISTRIBUTED COMPUTING AND APPLICATIONS TO BUSINESS, ENGINEERING AND SCIENCE (DCABES 2010), 1, 1, 615, 619
    DOI
  • High-Speed Modular Multipliers Based on a New Binary Signed-Digit Adder Tree Structure, Mingda Zhang,Shugang Wei, 2010年, PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON DISTRIBUTED COMPUTING AND APPLICATIONS TO BUSINESS, ENGINEERING AND SCIENCE (DCABES 2010), 1, 1, 615, 619
    DOI
  • Residue-Weighted Number Conversion with Moduli Set {2(p)-1, 2(p)+1, 2(2p)+1, 2(p)} Using Signed-Digit Number Arithmetic, Changjun Jiang,Shugang Wei, 2010年, PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON DISTRIBUTED COMPUTING AND APPLICATIONS TO BUSINESS, ENGINEERING AND SCIENCE (DCABES 2010), 1, 1, 629, 633
    DOI
  • Residue-Weighted Number Conversion with Moduli Set {2(p)-1, 2(p)+1, 2(2p)+1, 2(p)} Using Signed-Digit Number Arithmetic, Changjun Jiang,Shugang Wei, 2010年, PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON DISTRIBUTED COMPUTING AND APPLICATIONS TO BUSINESS, ENGINEERING AND SCIENCE (DCABES 2010), 1, 1, 629, 633
    DOI
  • Residue Signed-Digit Arithmetic and the Conversions between Residue and Binary Numbers for a Four-Moduli Set, Shugang Wei,Changjun Jiang, 2012年, 2012 11TH INTERNATIONAL SYMPOSIUM ON DISTRIBUTED COMPUTING AND APPLICATIONS TO BUSINESS, ENGINEERING & SCIENCE (DCABES), 436, 440
    DOI
  • Residue Signed-Digit Arithmetic and the Conversions between Residue and Binary Numbers for a Four-Moduli Set, Shugang Wei,Changjun Jiang, 2012年, 2012 11TH INTERNATIONAL SYMPOSIUM ON DISTRIBUTED COMPUTING AND APPLICATIONS TO BUSINESS, ENGINEERING & SCIENCE (DCABES), 436, 440
    DOI
  • Modulo (2(p) +/- 1) multipliers using a three-operand modular addition and booth recoding based on signed-digit number arithmetic, SG Wei,K Shimizu, 2003年, PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, V, 221, 224
  • Residue checker with signed-digit arithmetic for error detection of arithmetic circuits, SG Wei,K Shimizu, 2003年02月, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 12, 1, 41, 53
    DOI
  • Efficient squaring circuit using canonical signed-digit number representation, Yuuki Tanaka,Shugang Wei, 2014年, IEICE ELECTRONICS EXPRESS, 11, 2, 20130955
    DOI
  • Dynamic Range Compression Characteristics Using an Interpolatiog Polynomial for Digital Audio Systems, WEI SHUGANG, 2005年, IEICE TRANS. FUNDAMENTALS, 586-589
    DOI
  • Square-Rooting Algorithm Using Signed-Digit Arithmetic, WEI SHUGANG, 2005年, Proceedings of the 2005 International Technical Conference on Circuits/Systems, Computers and Communications, 599-600
  • Number Conversions between RNS and Mixed-Radix Number System Based on Modulo $(2^{p} - 1)$ Signed-Digit Arithmetic, WEI SHUGANG, 2005年, ACM proceedings of the 2005 Symposuim on Integrated Circuits and Systems Design, 160-165
    DOI
  • New Booth Modulo $m$ Multipliers with Signed-Digit Number Arithmetic, WEI SHUGANG, 2005年, IPSJ Journal, Vol. 46, no. 12, pp.3030-3039
  • Modulo $(2^{p} \pm 1)$ Multipliers Using a Three-Operand Modular Signed-Digit Addition Algorithm, WEI SHUGANG, 2006年, Journal of Circuits, Systems, and Computers, Vol. 15, no.1, pp.129-144
    DOI
  • Weighted-to-Residue and Residue-to-Weighted Converters with Three-Moduli $(2^n-1,2^n,2^n+1)$ Signed-Digit Architectures, WEI SHUGANG, 2006年, Proceedings of the 2006 IEEE Symposium on Circuits and Systems, pp.3365-3368
  • Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted NumberConverters with Moduli Set (2^n-1,2^n,2^n+1), WEI SHUGANG, 2006年, IPSJ Journal, Vol. 47, no. 6, pp.1884-1893
  • Audio Dynamic Range Compression Characteristics Based on an Interpolating Polynomial, WEI SHUGANG, 2004年, Proceedings of the 2nd Annual IEEE Northeast Workshop on Circuits and Systems, Vol.1, 133-136
  • A New RNS to Mixed-Radix Number Converter Using Modulo $(2^{p} - 1)$ Signed-Digit Arithmetic, WEI SHUGANG, 2004年, Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, Vol. 1, 377-380
  • Booth Memoryless Modular Multiplier with Signed-Digit Number Representation, WEI SHUGANG, 2004年, Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Syatems, Vol. 1, 21-24
  • Fast Modular Multiplication Using Booth Recoding Based on Signed-Digit Number Arithmetic, WEI SHUGANG, 2002年, Proceedings of 2002 IEEE Asia Pacific Conference On Circuits and Systems, 2,31-36
    DOI
  • Residue Checker with Signed -Digit Arithmetic for Error Detection of Arithmetic Circuits, WEI SHUGANG, 2003年, Journal of Circuits, Systems, and Computers, 12(1),41-53
    DOI
  • Residue Signed-Digit Arithmetic Circuit with a Complement of Mudulus and the Application to RSA Encryption Processor, WEI SHUGANG, 2002年, Proceedings of the 9th IEEE International Conference on Electronics, Circuits and Systems, 2, 591-294
    DOI
  • A VLSI Implementation Method of a Compressor for Audio Systems, WEI SHUGANG, 2001年, J. Acoust. Soc. Jpn.(E), 22, 407-414
    DOI
  • Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System, WEI SHUGANG, 2001年, Proceedings of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 72-77
  • Parallel Modular Arithmetic Based on Signed-Digit Number System and the Application to Error Detection of Product-Sum Computation, WEI SHUGANG, 2001年, Proceedings of the 2001 International Symposium on Distributed Computing and Applications to Business, Engineering and Science Electronics, Circuits and Systems, 19-23
  • Fast Residue Arithmetic Multipliers Based on Signed-Digit Number System, WEI SHUGANG, 2001年, Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems, (1), 263-266
  • Modular Multipliors Based on a Modified Booth Recoding Method With Signed-Digit Number Representation, WEI SHUGANG, 2003年, Proceedings of 2003 International Technical conference on Circuits/Systems, Computers and Communications, 1,559-564
  • Modulo (2p±1) Multiplier Using a Three-Operand Modular Addition and Booth Recoding Based on signed-Digit Number Arithmetic, WEI SHUGANG, 2003年, Proceedings of 2003 IEEE International Symposium on Circuits and Systems, 5,221-224
  • FPGA Design of Audio Signal Level Compressor, WEI SHUGANG, 2004年, Proceedings of the 2004 International Conference on Circuits/Systems, Computers and Communications, 7C1L-3, 1-4
  • A Multiplicative Inverse Algorithm Based on Modulo (2^p -1) Signed-Digit Arithmetic for Residue to Weighted Number Conversion, Shugang WEI, 2007年, Proceedings of 2007 IEEE International Symposium on Integrated Circuits, 25, 28
  • Acoustic Level Dynamic Compression Characteristics with FPGA Implementation, Shugang WEI,Wenhai XU, 2007年, Proceedings of the 7th WSEAS International Comference on Signal, Speech and Image Processing, 8, 13
  • Residue Checker with Signed-Digit Arithmetic for Error Detection of Arithmetic Circuits, Shugang Wei,Kensuke Shimizu, 2003年, Journal of Cricuits, Systems and Computers, 12, 1, 41, 53
    DOI
  • A Booth Recording Method for Serial Modular Multipliers with Signed-Digit Number Representation, WEI SHUGANG, 2002年, Proceedings of the 2002 International Conference on Fundamentals of Electronics, Communications and Computer Sciences, 2, 10-15
  • Design of Compressor/limiter on a digital signal processor, WEI SHUGANG, 1994年, The Journal of the Acoustical Society of Japan(J), 50/4,263-270
    DOI
  • Synthesis of Multilevel Feed-Forward NAND Netuorks, WEI SHUGANG, 1986年, IEICE Japan, J69-E/7,785-787
  • Synthesis of Multilevel Feed-Forward NOR Netuorks, WEI SHUGANG, 1987年, IEICE Japan, J70D/2,325-334
  • Residue Arithmetic Circuits Using a Signed-Digit Number Representation, WEI SHUGANG, 2000年, Proceedings of the IEEE 2000 International Symposium on circuits and Systems, (]G0001[)/,24-27
  • FPGA implementation of gain calculation using a polynomial expression for audio signal level dynamic compression, Shugang Wei,Wenhai Xu, 2008年, J.Acoust. Soc. Jpn.(E), Vol.29, No.6, 372, 377
    DOI
  • Dynamic Acoustic Signal Processing, WEI SHUGANG, 2000年, Proceedings of 2000 World Multi Conference on Systemics, Cybernetics and Informatics, (]G0006[)/,288-293
  • Residue Arithmetic with a Signed-Digit Number System, WEI SHUGANG, 2000年, Proceedings of 4th International Conference on High-Performance Computing, /,349-354
    DOI
  • Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation, WEI SHUGANG, 1999年, Proceedings of Ninth Great Lakes Symposium on VLSI, /,218
  • Residue Arithmetic Circuits Based on the Signed-Digit Multiple-Valued Arithmetic Circuits, WEI SHUGANG, 1998年, IEEE Proceedings of 28th International Symposium on Multiple-Valued Logic, /,276-281
  • Realization of over-easy characteristic of compressor/limiter on a digital signal processor, WEI SHUGANG, 1997年, J. Acoust. Soc. Jpn. (E), 18/2,59-66
    DOI
  • Modulo 2P-1 Arithmetic Hard wave Algorithm Using Signed-Digit Number Representation, WEI SHUGANG, 1996年, IEICE Japan, E79-D/3,242-246
  • Realization of Dynamic Range Controllers on a Digital Signal Processor for Audio Systems, WEI SHUGANG, 1995年, J. Acoust. Soc. Jpn.(E), 16/6,353-362
    DOI
  • Design of digital signal Level meter for audio systems based on the state transitions, WEI SHUGANG, 1995年, The Journal of the Acoustical Society of Japan(J), 51/4,291-298
    DOI
  • Design of an ASIC for digital audio signal Level meters, WEI SHUGANG, 1994年, IEEE Proceedings of Seventh Annual IEEE International ASIC Conference and Exhibit, /,288-291
  • Compact Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits, WEI SHUGANG, 1999年, IEICE TRANS ELECTRONICS, C82/9,1647-1954
  • Design of an RSA Encryption Processor Based on the Signed-Digit Multiple-Valued Arithmetic Circuits, WEI SHUGANG, 1990年, Scripta Technica Inc, 21/6,21-31
  • Performance Evaluation of a Multiple-Valued RSA Encryption VLSI, WEI SHUGANG, 1991年, Scriptn Technica Inc, 22/7,12-21
  • A Novel Residue Arithmetic Hardware Algorithm Using a Signed-Digit Number Representation, WEI SHUGANG, 2000年, IEICE TRANS.INF. & SYST., E83-D/12,2056-2064
  • Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Mutiple-Valued Arithmetic Circuits, WEI SHUGANG, 1999年, Proceldings of the 12th International Conference on VLSI Design, /,212
  • Modular multipliers Using a Modified Residue Addition Algorithm with Signed-Digit Number Representation, Shugang Wei, 2009年, Lecture Notes in Engineering and Computer Science, International MultiConference of Engineers and Computer Scientists 2009, Vol. 1, 494, 499
  • A New Residue Adder with Redundant Binary Number Representation, Shugang Wei, 2008年, Proceedings of the 6th Annual IEEE Northeast Workshop on Circuits and Systems, 157, 160
  • Efficient Residue Checker Using New Binary Modular Adder Tree Structure for Arithmetic of Error Detection, M. Zhang,S. Wei, 2011年, Proceedings of Eighth International Conference on Fuzzy Systems and Knowledge Discovery, 2481, 2485
  • Sequential Modular Multipliers Using Residue Signed-Digit Additions, S. Wei, 2012年, Journal of Communication and Computer, 9, 8, 872, 878
  • A Sequential Modular Multiplication Algorithm Using Signed-Digit Additions, S. Wei, 2011年, IEEE Proceedings of TENCON2011, 370, 374
  • Residue-Weighted Number Conversion for Moduli Set {2^2n-1, 2^2n+1+1, 2^n} Using Signed-Digit Number, C. Jiang,S. Wei, 2012年, Proceedings of the 10th Annual IEEE Northeast Workshop on Circuits and Systems, 9, 12
  • An RSA encryption Implementation Method Using Signed-Digit Arithmetic Circuits, S. Wei, 2012年, IEEE Proceedings of 5th International Conference on Biomedical Engineering and Informatics, 1337, 1341
  • Residue-Binary Number Conversion Using Signed-Digit Arithmetic for a Three-Moduli Set, S. Wei, 2012年, IEEE Proceedings of TENCON2012, 371, 374
  • An Advanced Implementation of Canonical Signed-Digit Recoding Circuit, Tanaka\, Yuuki,Wei\, Shugang, 2013年, Journal of Communication and Computer, 10, 11, 1396, 1402
  • Efficient Implementations of Canonical Signed-Digit Recoding Algorithm, Tanaka Y,Zhang Y,Wei S, 2013年, Proceedings of ICDV2013, 67, 72
  • Recoding Algorithms for Minimal Signed-Digit Numbers in Residue Number System, Zhang Y,Tanaka Y,Wei S, 2013年, IEEE Proceedings of TENCON2013
    DOI
  • New Binary Modular Adder Tree Structure for Arithmetic of Error Checker of Arithmetic, Zhang M,Wei S, 2013年, Journal of Communication and Computer, 10, 3, 295, 300
  • Residue Checker Using Optimal Signed-Digit Adder Tree for Error Detection of Arithmetic Circuits, Wei S, 2014年, IEEE Proceedings of TENCON2014
    DOI
  • Conversions between RNS and Mixed-Radix Numbers Using Signed-Digit Arithmetic, Wei S, 2014年, IEEE Proceedings of ISIC-2014, 600, 603
    DOI
  • An Efficient Diminished-1 Modulo 2n + 1 Multiplier Using Signed-Digit Number Representation, Tanaka Y. Wei S, 2015年, IEEE Proceedings of TENCON2015, 1-6.
  • Fast Signed-Digit Architectures of Conversions Between Residue and Binary Number Systems, Wei S, 2015年, Proceedings of 2015 IEEE Intl Conference on Electronics, Circuits, & Systems, 1-4.
  • Computation of Modular Multiplicative Inverses Using Residue Signed-Digit Additions, Wei S, 2016年, Proceedings of 2016 International SoC Design Conference, 1-4.
  • Residue Canonical Signed-Digit Representation Recoding Algorithms, Zhang Y,Tanaka Y,Wei S, 2016年, Journal of Algorithms, Computer Network, and Security, 1, 1, 1-7.
  • New Modulo Multipliers Using Residue Signed-Digit Adders, Wei S, 2017年, IEEE Proceedings of TENCON2017, 1-5.
  • RSA暗号処理のための剰余演算回路, 魏 書剛, 2002年, 電子情報通信学会信学技報VLD2001, 9-16
  • Dynamic Range Compression Characteristics Using an Interpolatiog Polynomial for Digital Audio Systems, WEI SHUGANG, 2005年, IEICE TRANS. FUNDAMENTALS, 586-589
    DOI
  • Square-Rooting Algorithm Using Signed-Digit Arithmetic, WEI SHUGANG, 2005年, Proceedings of the 2005 International Technical Conference on Circuits/Systems, Computers and Communications, 599-600
  • Number Conversions between RNS and Mixed-Radix Number System Based on Modulo $(2^{p} - 1)$ Signed-Digit Arithmetic, WEI SHUGANG, 2005年, ACM proceedings of the 2005 Symposuim on Integrated Circuits and Systems Design, 160-165
    DOI
  • New Booth Modulo $m$ Multipliers with Signed-Digit Number Arithmetic, WEI SHUGANG, 2005年, IPSJ Journal, Vol. 46, no. 12, pp.3030-3039
  • Modulo $(2^{p} \pm 1)$ Multipliers Using a Three-Operand Modular Signed-Digit Addition Algorithm, WEI SHUGANG, 2006年, Journal of Circuits, Systems, and Computers, Vol. 15, no.1, pp.129-144
    DOI
  • Weighted-to-Residue and Residue-to-Weighted Converters with Three-Moduli $(2^n-1,2^n,2^n+1)$ Signed-Digit Architectures, WEI SHUGANG, 2006年, Proceedings of the 2006 IEEE Symposium on Circuits and Systems, pp.3365-3368
  • Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted NumberConverters with Moduli Set (2^n-1,2^n,2^n+1), WEI SHUGANG, 2006年, IPSJ Journal, Vol. 47, no. 6, pp.1884-1893
  • SD数演算を用いた剰余数系ー重み数系変換回路, 魏 書剛, 2005年, 電子情報通信学会信学技報VLD2004, VLD2004-123,79-84
  • Audio Dynamic Range Compression Characteristics Based on an Interpolating Polynomial, WEI SHUGANG, 2004年, Proceedings of the 2nd Annual IEEE Northeast Workshop on Circuits and Systems, Vol.1, 133-136
  • A New RNS to Mixed-Radix Number Converter Using Modulo $(2^{p} - 1)$ Signed-Digit Arithmetic, WEI SHUGANG, 2004年, Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, Vol. 1, 377-380
  • Booth Memoryless Modular Multiplier with Signed-Digit Number Representation, WEI SHUGANG, 2004年, Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Syatems, Vol. 1, 21-24
  • Fast Modular Multiplication Using Booth Recoding Based on Signed-Digit Number Arithmetic, WEI SHUGANG, 2002年, Proceedings of 2002 IEEE Asia Pacific Conference On Circuits and Systems, 2,31-36
    DOI
  • Residue Checker with Signed -Digit Arithmetic for Error Detection of Arithmetic Circuits, WEI SHUGANG, 2003年, Journal of Circuits, Systems, and Computers, 12(1),41-53
    DOI
  • Residue Signed-Digit Arithmetic Circuit with a Complement of Mudulus and the Application to RSA Encryption Processor, WEI SHUGANG, 2002年, Proceedings of the 9th IEEE International Conference on Electronics, Circuits and Systems, 2, 591-294
    DOI
  • A VLSI Implementation Method of a Compressor for Audio Systems, WEI SHUGANG, 2001年, J. Acoust. Soc. Jpn.(E), 22, 407-414
    DOI
  • Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System, WEI SHUGANG, 2001年, Proceedings of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 72-77
  • Parallel Modular Arithmetic Based on Signed-Digit Number System and the Application to Error Detection of Product-Sum Computation, WEI SHUGANG, 2001年, Proceedings of the 2001 International Symposium on Distributed Computing and Applications to Business, Engineering and Science Electronics, Circuits and Systems, 19-23
  • Fast Residue Arithmetic Multipliers Based on Signed-Digit Number System, WEI SHUGANG, 2001年, Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems, (1), 263-266
  • Modular Multipliors Based on a Modified Booth Recoding Method With Signed-Digit Number Representation, WEI SHUGANG, 2003年, Proceedings of 2003 International Technical conference on Circuits/Systems, Computers and Communications, 1,559-564
  • FPGAを用いた音響信号レベル圧縮プロセッサの設計, 魏 書剛, 2003年, 電子情報通信学会研究会技報, VLD2003-66,77-82
  • SD数演算を用いた２進浮動小数点加算回路構成, 魏 書剛, 2002年, 電子情報通信学会信学技報, VLD2002-132,13-18
  • Modulo (2p±1) Multiplier Using a Three-Operand Modular Addition and Booth Recoding Based on signed-Digit Number Arithmetic, WEI SHUGANG, 2003年, Proceedings of 2003 IEEE International Symposium on Circuits and Systems, 5,221-224
  • FPGA Design of Audio Signal Level Compressor, WEI SHUGANG, 2004年, Proceedings of the 2004 International Conference on Circuits/Systems, Computers and Communications, 7C1L-3, 1-4
  • A Multiplicative Inverse Algorithm Based on Modulo (2^p -1) Signed-Digit Arithmetic for Residue to Weighted Number Conversion, Shugang WEI, 2007年, Proceedings of 2007 IEEE International Symposium on Integrated Circuits, 25, 28
  • Acoustic Level Dynamic Compression Characteristics with FPGA Implementation, Shugang WEI,Wenhai XU, 2007年, Proceedings of the 7th WSEAS International Comference on Signal, Speech and Image Processing, 8, 13
  • Modulo (2~p +-1) Multipliers Using Three-Operand Modular Addition and Booth Recoding Based on Signed-Digit Number Arithmetic, Shugang Wei,Kensuke Shimizu, 2003年, Proceedings of the 2003 IEEE Symposium on Circuits and Systems, V, 221, 224
  • A Booth Recording Method for Serial Modular Multipliers with Signed-Digit Number Representation, WEI SHUGANG, 2002年, Proceedings of the 2002 International Conference on Fundamentals of Electronics, Communications and Computer Sciences, 2, 10-15
  • Design of Compressor/limiter on a digital signal processor, WEI SHUGANG, 1994年, The Journal of the Acoustical Society of Japan(J), 50/4,263-270
    DOI
  • Synthesis of Multilevel Feed-Forward NAND Netuorks, WEI SHUGANG, 1986年, IEICE Japan, J69-E/7,785-787
  • Synthesis of Multilevel Feed-Forward NOR Netuorks, WEI SHUGANG, 1987年, IEICE Japan, J70D/2,325-334
  • 多値RSA暗号処理VLSIの性能評価, 魏 書剛, 1991年, 22/7,12-21
  • Residue Arithmetic Circuits Using a Signed-Digit Number Representation, WEI SHUGANG, 2000年, Proceedings of the IEEE 2000 International Symposium on circuits and Systems, (]G0001[)/,24-27
  • FPGA implementation of gain calculation using a polynomial expression for audio signal level dynamic compression, Shugang Wei,Wenhai Xu, 2008年, J.Acoust. Soc. Jpn.(E), Vol.29, No.6, 372, 377
    DOI
  • 多段フィードフォワードNAND回路網の設計, 魏 書剛, 1986年, J69-E/7,785-787
  • コンプレッサ/リミッタのDSPによる実現法, 魏 書剛, 1994年, 日本音響学会誌, 50/4,263-270
    DOI
  • 状態遷移に基づくディジタル音響信号レベル表示回路の構成, 魏 書剛, 1995年, 日本音響学会誌, 51/4,291-298
    DOI
  • Dynamic Acoustic Signal Processing, WEI SHUGANG, 2000年, Proceedings of 2000 World Multi Conference on Systemics, Cybernetics and Informatics, (]G0006[)/,288-293
  • Residue Arithmetic with a Signed-Digit Number System, WEI SHUGANG, 2000年, Proceedings of 4th International Conference on High-Performance Computing, /,349-354
    DOI
  • Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation, WEI SHUGANG, 1999年, Proceedings of Ninth Great Lakes Symposium on VLSI, /,218
  • Residue Arithmetic Circuits Based on the Signed-Digit Multiple-Valued Arithmetic Circuits, WEI SHUGANG, 1998年, IEEE Proceedings of 28th International Symposium on Multiple-Valued Logic, /,276-281
  • Realization of over-easy characteristic of compressor/limiter on a digital signal processor, WEI SHUGANG, 1997年, J. Acoust. Soc. Jpn. (E), 18/2,59-66
    DOI
  • Modulo 2P-1 Arithmetic Hard wave Algorithm Using Signed-Digit Number Representation, WEI SHUGANG, 1996年, IEICE Japan, E79-D/3,242-246
  • Realization of Dynamic Range Controllers on a Digital Signal Processor for Audio Systems, WEI SHUGANG, 1995年, J. Acoust. Soc. Jpn.(E), 16/6,353-362
    DOI
  • Design of digital signal Level meter for audio systems based on the state transitions, WEI SHUGANG, 1995年, The Journal of the Acoustical Society of Japan(J), 51/4,291-298
    DOI
  • Design of an ASIC for digital audio signal Level meters, WEI SHUGANG, 1994年, IEEE Proceedings of Seventh Annual IEEE International ASIC Conference and Exhibit, /,288-291
  • Compact Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits, WEI SHUGANG, 1999年, IEICE TRANS ELECTRONICS, C82/9,1647-1954
  • Design of an RSA Encryption Processor Based on the Signed-Digit Multiple-Valued Arithmetic Circuits, WEI SHUGANG, 1990年, Scripta Technica Inc, 21/6,21-31
  • Performance Evaluation of a Multiple-Valued RSA Encryption VLSI, WEI SHUGANG, 1991年, Scriptn Technica Inc, 22/7,12-21
  • Signed-Digit数多値演算回路に基づくRSA暗号処理プロセッサの構成, 魏 書剛, 1990年, 21/6,21-31
  • A Novel Residue Arithmetic Hardware Algorithm Using a Signed-Digit Number Representation, WEI SHUGANG, 2000年, IEICE TRANS.INF. & SYST., E83-D/12,2056-2064
  • Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Mutiple-Valued Arithmetic Circuits, WEI SHUGANG, 1999年, Proceldings of the 12th International Conference on VLSI Design, /,212
  • 多段フィードフォワードNOR回路網の一設計法, 魏 書剛, 1987年, J70D/2,325-334
  • Efficient Residue Checker Using New Binary Modular Adder Tree Structure for Arithmetic of Error Detection, M. Zhang,S. Wei, 2011年, Proceedings of Eighth International Conference on Fuzzy Systems and Knowledge Discovery, 2481, 2485
  • Sequential Modular Multipliers Using Residue Signed-Digit Additions, S. Wei, 2012年, Journal of Communication and Computer, 9, 8, 872, 878
  • A Sequential Modular Multiplication Algorithm Using Signed-Digit Additions, S. Wei, 2011年, IEEE Proceedings of TENCON2011, 370, 374
  • ＳＤ数演算を用いた剰余数系ー２進数系変換アルゴリズム, 姜 長シュン,魏 書剛, 2010年, 電子情報通信学会研究報告, VLD2009-80, 71, 76
  • ＳＤ数表現を用いた剰余演算回路設計とその性能評価, 張 明達,魏 書剛, 2010年, 電子情報通信学会研究報告, VLD2009-80
  • 最小ＳＤ数表現を用いた剰余演算とＦＩＲフィルタ回路への応用, 陳睿,田中勇樹,魏 書剛, 2011年, 電子情報通信学会研究報告, VLD2010-96, 75, 80
  • 多項式表現のゲインを用いた音響信号レベル圧縮特性, 宮下達也,茂木和弘,魏 書剛, 2011年, 電子情報通信学会研究報告, VLD2010-96, 81, 85
  • ＳＤ数演算を剰余数系―重み数系変換アルゴリズム, 新井聖哉,田中勇樹,魏 書剛, 2012年, 電子情報通信学会研究報告, 2011-110, 111, 116
  • ２分木構造の剰余ＳＤ数演算を用いた算術演算エラー検出回路, 劉茜,茂木和弘,魏 書剛, 2012年, 電子情報通信学会研究報告, VLD2011-110, 117, 121
  • 剰余SD数の非零桁数を削減する変換アルゴリズム, 田中勇喜,魏書剛, 2012年, 第２５回 回路とシステムワークショップ, 156, 159
  • Residue-Weighted Number Conversion for Moduli Set {2^2n-1, 2^2n+1+1, 2^n} Using Signed-Digit Number, C. Jiang,S. Wei, 2012年, Proceedings of the 10th Annual IEEE Northeast Workshop on Circuits and Systems, 9, 12
  • An RSA encryption Implementation Method Using Signed-Digit Arithmetic Circuits, S. Wei, 2012年, IEEE Proceedings of 5th International Conference on Biomedical Engineering and Informatics, 1337, 1341
  • Residue-Binary Number Conversion Using Signed-Digit Arithmetic for a Three-Moduli Set, S. Wei, 2012年, IEEE Proceedings of TENCON2012, 371, 374
  • SD数の非零桁削減回路の改良, 田中 勇喜,魏 書剛, 2013年, 第２６回 回路とシステムワークショップ, 209, 214
  • ＳＤ数の２値符号化による算術演算回路の最適化設計と性能評価, 小林拓矢,茂木和弘,魏 書剛, 2013年, 電子情報通信学会研究報告, VLD-2012, 114, 39, 44
  • ＳＤ数演算を用いたＲＳＡ暗号処理回路の設計と性能評価, 浅岡隼一,田中勇樹,魏 書剛, 2013年, 電子情報通信学会研究報告, VLD-2012, 115, 45, 50
  • An Advanced Implementation of Canonical Signed-Digit Recoding Circuit, Tanaka\, Yuuki,Wei\, Shugang, 2013年, Journal of Communication and Computer, 10, 11, 1396, 1402
  • Efficient Implementations of Canonical Signed-Digit Recoding Algorithm, Tanaka Y,Zhang Y,Wei S, 2013年, Proceedings of ICDV2013, 67, 72
  • Recoding Algorithms for Minimal Signed-Digit Numbers in Residue Number System, Zhang Y,Tanaka Y,Wei S, 2013年, IEEE Proceedings of TENCON2013
    DOI
  • New Binary Modular Adder Tree Structure for Arithmetic of Error Checker of Arithmetic, Zhang M,Wei S, 2013年, Journal of Communication and Computer, 10, 3, 295, 300
  • Efficient squaring circuit using canonical signed-digit number representation, Tanaka\, Yuuki,Wei\, Shugang, 2014年, IEICE ELECTRONICS EXPRESS, 11, 2, 20130955
    DOI
  • Residue Checker Using Optimal Signed-Digit Adder Tree for Error Detection of Arithmetic Circuits, Wei S, 2014年, IEEE Proceedings of TENCON2014
    DOI
  • Conversions between RNS and Mixed-Radix Numbers Using Signed-Digit Arithmetic, Wei S, 2014年, IEEE Proceedings of ISIC-2014, 600, 603
    DOI
  • 剰余SD数演算回路を用いた算術演算誤り検出, 根間裕智,田中勇樹,魏 書剛, 2015年, 電子情報通信学会研究報告, VLD2014, 136, 151, 156
  • An Efficient Diminished-1 Modulo 2n + 1 Multiplier Using Signed-Digit Number Representation, Tanaka Y. Wei S, 2015年, IEEE Proceedings of TENCON2015, 1-6.
  • Fast Signed-Digit Architectures of Conversions Between Residue and Binary Number Systems, Wei S, 2015年, Proceedings of 2015 IEEE Intl Conference on Electronics, Circuits, & Systems, 1-4.
  • Computation of Modular Multiplicative Inverses Using Residue Signed-Digit Additions, Wei S, 2016年, Proceedings of 2016 International SoC Design Conference, 1-4.
  • 法2n-1上の剰余CSD数表現と剰余SD数乗算への適用, 田中勇樹,中村康資,魏 書剛, 2016年, 第29回回路とシステムワークショップ, 231, 236
  • Residue Canonical Signed-Digit Representation Recoding Algorithms, Zhang Y,Tanaka Y,Wei S, 2016年, Journal of Algorithms, Computer Network, and Security, 1, 1, 1-7.
  • 新しい剰余SD数加算アルゴリズムとRSA暗号処理への応用, 石川和誠,田中勇樹,魏 書剛, 2017年, 電子情報通信学会研究報告, VLD2016, 92, 147, 152
  • New Modulo Multipliers Using Residue Signed-Digit Adders, Wei S, 2017年, IEEE Proceedings of TENCON2017, 1-5.
  • SD数演算に基づく4つの法を有する剰余数系?重み数系変換アルゴリズム, 山崎幸平,田中勇樹,魏 書剛, 2018年, 電子情報通信学会研究報告, VLD2017, 88, 83, 88

書籍等出版物

  • 情報・システム入門, 東京図書, 1996年

講演・口頭発表等

  • ＳＤ数剰余加算を用いた剰余除算回路の構成, 電子情報通信学会ＶＬＤ研究会, 2007年
  • ＦＰＧＡを用いた音響信号レベル圧縮プロセッサの設計, 電子情報通信学会ＶＬＤ研究会, 2003年
  • そろばんアーキテクチャに基づく算術演算回路, 電子情報通信学会研究報告, ICD2008, 2008年
  • 算盤アーキテクチャを用いた10進加算器とその剰余演算への応用, 電子情報通信学会研究報告, DC2008, 2009年
  • ＳＤ数演算を用いた剰余数系ー２進数系変換アルゴリズム, 電子情報通信学会研究報告, 2010年
  • ＳＤ数表現を用いた剰余演算回路設計とその性能評価, 電子情報通信学会研究報告, VLD2009-80, 2010年

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